Title: Standard for Quantum Computing Energy Efficiency
Scope: This standard defines energy efficiency metrics for quantum computing (gate-based, quantum annealing, quantum simulation). It compares the performance of the computation to its energy consumption. The performance is defined at the quantum level and at the end user level. The definition applies to all Quantum Bit (qubit) technologies, including the classical and quantum control chains, to various quantum processors, both Noisy Intermediate Scale Quantum (NISQ)-era and fault-tolerant, as well as to quantum annealers and simulators.
Please subscribe to the IEEE P3329 QEI Working Group public e-mail reflector for additional information.
Next working group meeting: 27th March 2024 11am-13:30pm CET
Abstract of Jeremy’s talk:
“In a world of finite resources, the development of new technologies should carefully balance performance and energetic cost. So far only a minority of works consider the ressource cost of computing with qubits, with most of the literature focusing on performance. In my talk I will present some first steps towards accounting for the ressource cost of dissipative cat qubits. I will detail the current energy budget and pin-point certain inefficiencies by deep diving into the hardware physics all the way down to the interaction Hamiltonian. This example study on a specific hardware approach may form the basis for a more generic framework, which could inspire a standardised approach valid for other technologies.”
The draft agenda is accessible here: IEEE_P3329_QEI_WG_DraftAgenda_march2024
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Below: old meetings previously announced on the website.
Next working group meeting: 23’th February 2024 12pm-13:00pm CET
Next working group meeting: 28’th November 2023 11am-12:30pm CET
The next meeting of the Working Group will be devoted to a presentation by Adrien Suau and Jean Baptiste Latre which abstract is written below. The Draft Meeting Agenda is accessible here: IEEE_P3329_QEI_WG_DraftAgenda_december2023
The zoom link will be: https://univ-grenoble-alpes-fr.zoom.us/j/97543849951?pwd=OVc2SnVvM00va0Z4ZWV2T05kUnhSQT09
Update: the zoom link will actually be this one: https://us06web.zoom.us/j/87378746121?pwd=BcyWgeHupaM8WVNEYk9Ea8sqJ3caQJ.1
The abstract is written below:
Impact of software and algorithms in quantum computing energy efficiency
This talk is about challenges that arise higher in the quantum computing stack than hardware and that may severely impact the energetic efficiency of quantum chips if not considered.
The efficiency of quantum computations relies on an appropriate co-design between hardware and software. While the effect of hardware on software is commonly admitted, a complete co-design approach is bidirectional. Therefore, one should also consider the influence of practical use cases and software on the hardware design.
Failing to do so may produce “efficient” hardware for which quantum algorithm implementation will have to be deeply changed and adapted to run, impacting the whole stack efficiency.
Overall, the total cost of practical and explicit quantum algorithm implementation, taking into account qubit architecture, native gate conversion and algorithmic black-boxes (among other) can overweight theoretical speed-ups.
It is also enlightening to consider the impact of software in the energetic efficiency explaining why quantum computing is not ready yet for high level programming. Learning from classical computing, it turns out that higher-level programming languages can consume up to two order of magnitude more energy than their lower-level counter part. This ratio calls for an effort in making the hardware easily controllable by the programmer to avoid inefficiencies that can be up to several order of magnitude.
To be complete and even if it is a huge technical challenge, the global energetic efficiency of quantum computing should also take into account the associated cost of High Performance Computing (HPC).
Next working group meeting:
The next meeting of the Working Group will be devoted to a presentation by Erik P. DeBenedictis on how reversible transistor logic and Josephson junction logic could improve the energy efficiency of quantum computers, and how such approaches could help defining an energy standard. It will happen the Friday 22 of September, from 11:00 to 12:30 CET: please save the date in your agendas. The Draft Meeting Agenda is accessible here: IEEE_P3329_QEI_WG_DraftAgenda_22_september
The more detailed abstract is written below:
Title: How to improve quantum energy efficiency and how standards could help
Speaker: Erik P. DeBenedictis, Zettaflops, LLC
This is a talk about reversible (transistor) logic and Josephson junction logic.
In the previous meeting, Marco Fellous-Asiani discussed how to predict quantum computer energy consumption based on parameters of classical circuits, qubits, and algorithms. This talk will discuss how to reduce this energy consumption. Marco’s results reveal the dissipation of cryo-CMOS’s is a predominant factor, so the basic approach is to reduce the dissipation of the digital component. Marco’s thesis describes the options as reversible and Josephson junction logic. This talk will explore these alternatives, recent results, and potential standards.
Reversible (transistor) logic is created on the same fab line as CMOS, yet uses a different logic circuit design. In a cryogenic environment, most of the waste heat from the reversible circuit is transferred to room temperature electrically in a wire, bypassing the cryocooler and its overhead, and potentially reducing wall-plug power by 100x.
Energy levels for Josephson logic are about a million times lower than CMOS, yet Josephson junctions are physically huge compared to transistors, reducing maximum circuit complexity. Recent research funding calls are starting to ask for hybrid Josephson-CMOS integration, where the hybrids could approach CMOS complexity levels while approaching Josephson energy levels.
Zettaflops, LLC has simulations and layouts for reversible transistor circuits in an architecture that could address quantum computer control. While chips have yet to be fabbed, some of the layout IP could be available as open source (https://revcomp.org).
The considerations above could lead to standards. Intel’s Horse Ridge and IBM’s (unnamed) cryo-CMOS chips have a dissipation of around 25 mW/qubit, yet we will argue that widespread commercial success of quantum computers would need about a 25,000x reduction. A possible P3329 standard would define one or more subsystems for qubit control and a uniform way of measuring dissipation. This standard could be used by innovators creating successive generations of control circuits that progressively reduce dissipation from current levels.
Speaker is Erik P. DeBenedictis. Erik holds degrees in EE and CS and has worked at Bell Labs, Ansoft (now Ansys), nCUBE Corp., NetAlive, Inc., and Sandia Labs. Erik is now principal of Zettaflops, LLC http://zettaflops.org developing technology and IP for quantum computer control. Erik lives in New Mexico, USA.