Call to action: the IEEE 1149.1 working group is soliciting comments and feedback from the test community.
Title: Standard for Test Access Port and Boundary-Scan Architecture
Scope:
This standard defines test logic that can be included in an integrated circuit (IC), as well as structural and procedural description languages, to provide standardized approaches to
- testing the interconnections between integrated circuits once they have been assembled onto a printed circuit board (PCB) or other substrate;
- testing the integrated circuit itself; and
- observing, modifying, or loading data inside an integrated circuit during test, programming, configuration, or debug of the integrated circuit or the circuitry connected to the component.
Purpose:
The purpose of this standard is to facilitate test access to board-level interconnects from standardized chip-embedded test resources, overcoming the lack of test access with physical probing methods. The design-for-testability (DFT) features defined in this standard provide a serial digital access method. This architecture allows for the ability to control and/or observe data inside an integrated circuit for a variety of applications. These applications include, but are not limited to, testing, programming, configuring, and debugging intellectual property (IP) blocks and logic contained within that integrated circuit.
The standard provides domain-specific languages required to support the defined architecture and the targeted applications.
Need:
Testing of assembled printed circuit boards and other products based on highly complex digital integrated circuits and high-density, surface-mounting assembly techniques has become extremely difficult due to test access limitations. Similar difficulties are faced by equipment used for the test of integrated circuits in the production of known-good die (KGD) required for complex system-in-package (SiP) technologies. Other standards, such as subordinate IEEE 1149 standards and related test technology standards IEEE Std 1500, IEEE Std 1532, IEEE Std 1687, and IEEE Std 1838, rely on this standard and its defined Test Access Port (TAP) to provide access to and control of features built into integrated circuits.
