To aid general improvement and comparison of mixed-signal DFT methods and tools, including analog fault simulation, a set of analog, mixed-signal, and digital circuits are available for free. The initial cells were created by ams AG and Mentor. Additional contributions that use the same process files and operating conditions are welcome. Address any correspondence to [email protected].
VERSION 2.0 INCLUDES: (ITC 2017 AMS Benchmark Circuits)
• CMOS process device models, including typical and 4 corners, derived from ams’s 350 nm process
• SPICE netlists for 9 commonly used analog and mixed-signal functions (6 complex functions and 3 transmission gates)
• SPICE netlists and Verilog models for 42 basic combinational and sequential logic gates
• Testbenches for the functions and gates, including specifications with limits for operation at 3.3V, 27C
Download a compressed file of Version 2.0 containing a Linux® directory and all files
VERSION 2.1 INCLUDES: (ITC 2017 AMS Benchmark Circuits)
Same files as Version 2.0 plus:
• SPICE netlists for two additional circuits: PLL and ADC
• Schematic diagrams for each A/MS netlist
• List of potential defects for each A/MS netlist, with area-based likelihoods
• Specifications and additional testbench for the op-amp and comparator
• Updated README file
Download a compressed file of Version 2.1 containing a Linux® directory and all files
VERSION 2.2 INCLUDES: (ITC 2017 AMS Benchmark Circuits)
Same files as Version 2.1 plus:
• SPICE netlist for one additional circuit: VREG1
• Corrected models for several logic gates in LOGIC.v
• Corrected BANDGAP1, OPAMP1, and PLL1 testbenches
• For BANDGAP1, collapsed parallel transistors into single transistors, each with increased m (multiplier), consistent with IEEE P2427 proposed rules
• Updated README file
Download a compressed file of Version 2.2 containing a Linux® directory and all files
VERSION 3.0 INCLUDES: (Infineon AMS Benchmark Circuits)
• Four circuit examples: BANDGAP, LDO, PLL and SARADC
• Hspice netlist and testbench for all the circuits
• Nominal, fast and slow process corner models for all the circuits
• Defect list for all the circuits
• Spec document along with a readme file for all the circuits
Download a compressed file of Version 3.0
VERSION 4.0 INCLUDES: (Infineon AMS Benchmark Circuits)
• Five circuit examples: BANDGAP, LDO, PLL, SARADC and PHY (new addition)
• Hspice netlist and testbench for all the circuits
• Nominal, fast and slow process corner models for all the circuits
• Defect list have been removed except bandgap. Defect list for other circuits to be regenerated and re-released later.
• Spec document along with a readme file for all the circuits
Download a compressed file of Version 4.0
Github repo for Infineon AMS benchmark circuits: https://github.com/Infineon/adsbenchmark
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