IEEE 2929
P2929 - Standard for System-level State Extraction for Functional Validation and Debug (C/TT/Scan and Array Debug)

IEEE P2929 Scope, Purpose and Need

Scope of the Proposed IEEE P2929 Standard:  

  • This standard leverages existing standards-based test access mechanisms to capture and retrieve flip-flop and array/memory states. This standard defines a methodology for scan and memory/array debug data extraction for effective functional debug of System-on-Chip (SoC) and addresses other essential architectural modifications needed to support this, such as power-management changes. This standard provides a reliable and consistent methodology on trigger-based freezing of SoC scan and array states, and retrieval of those states.

Purpose of the Proposed IEEE P2929 Standard:  

  • The methodology described allows simpler and quicker debugging of hardware and software, software testing, and performance analysis. Its output data format supports Machine Learning, Artificial Intelligence, and other efficient algorithms. Lastly, the methodology supports development of better Electronic Design Automation (EDA) tools to accomplish these tasks

Need for the Proposed IEEE P2929 Standard:  

  • System-on-Chip (SoC) debug requires observing the states of the SoC’s internal flip-flops and arrays/memories. Most modern SoC designs implement scan-based design to reduce the complexity of sequential testing to combinational testing and implementing memory Built-In Self-Test (BIST) for testing memories/arrays. For functional debug of SoCs, state analysis of flip-flops and memories/arrays is needed that extracts states via existing standards-based test infrastructures. Additional mechanisms are needed within SoCs to capture states at specific times prior to extraction. The existing IEEE Standards 1149.1, 1500, or 1687 do not address internal state (Scan and/or Array/Memory) extraction for debug purposes. System-on-Chip (SoC) silicon debug engineers have always needed the capability of making the internal states of scan elements and arrays/memories observable, but there is no existing standard methodology that facilitates this. Hence, scan and array debug extraction has been implemented in an AdHoc manner that has not been successful consistently even among teams of the same company. Developing a standard for scan and array debug extraction will greatly help the SoC industry and will enable the EDA industry to develop improved debug tools. Furthermore, a common debug data format will aid analysis of vast amounts of debug data collected for performing Machine Learning/Deep Learning.